Lab 6 - EE 421L 

Authored by Luis A. Soriano,

Email: sorian20@unlv.nevada.edu

Date: October 19, 2015

Lab Report - Design, layout, and simulation of CMOS NAND gate, XOR gate, and Full-Adder

Pre-Lab: Following Tutorial 4, we were to create the schematic, symbol, simulation, layout, and LVS of a NAND gate. To do so, the previous Tutorial_3 is copied to a newlibrary called 'Tutorial_4'; and the 'inverter' cell, to a cell called nand2. Based on the inverter cell, we edited the schematic to design a NAND gate, as shown below.

Note that this NAND gate uses 6u/0.6u MOSFETS for both NMOS and PMOS. Then, the symbol is created.

Next, we use the symbol to simulate our NAND gate and verify it works properly.

'Check and Save' to make sure the 'vdd' and NAND symbol do not overlap.

Making sure that the corresponding nmos and pmos models are added, simulation is perfromed.

Now that simulation matches our expected results, we can layout the NAND gate as seen below. Then, we can extract it.

DRC the layout to verify that any rule was violated.

Note that, since the metal1 connection between NMOS devices were not needed, I just removed it using Edit-> Hierarchy->Flatten to convert NMOS cells in rectangles.

For some reason, tutorial 4 shows 12u/0.6u PMOS devices in the layout. However, since 6u/0.6u PMOS devices were used in the schematics and simulations, and further in laboratory experiments, I laid out NAND gate with 6u/0.6u MOSFETS for both NMOS and PMOS. Moreover, I modified the previous layout in this prelab, so it matches the lab requirements (see below).

Next to the above layout, the extracted view is shown. This NAND gate layout will be used later in the lab experiment report. Now, LVS (layout vs schematic) is performed.

--------------------------------------------------------------------------------------------------------------------

Post Lab Report

Lab description: In this laboratory exercise, we were to draft the schematics and symbols, simulate, layout, and LVS a 2-input NAND gate, 2-input XOR gate, and a Full Adder.

I made use of my NAND cells created in the prelab, so I start by copying them to a new library called 'Lab6' and renamed it as NAND_ls_f15, per lab requirements. Again, the schematic, symbol, and layout are shown below. Note that I named the symbol as NAND_LS.

Next, the schematic for XOR gate is drafted as follows.

'Check and save' to ensure no connection errors in the schematic.

Now, the symbol is created and named as XOR_LS as seen below.

The XOR gate is laid out as shown below

However, according to the lab requirements, I modified the mayout and used a much higher standard cell height.

DRC to verify no rules were violated.

It is worth to mention that I had a hard time trying to interconnect the MOSFETs. At the end, I decided to make most of the connections in the n-well layer of the PMOS devices, so there is more space between NMOS and PMOS devices. Also, I used the metal2 layer to route over metal 1 layer and avoid overlapping. Finally, bigger ntap and ptap were used for vddd and gnd, repectively, connected to metal1 layer to avoid ground bouncing. Now, the extracted layout and corresponding LVS is shown below. The LVS (layout vs schematic)shows that both netlists matched.

Now, I can proceed with the simulation of the NAND gate, XOR gate, and inverter to verify that the following truth table is satistfied. 

The inverter was copied from the previous lab 3 added to Lab6, per lab requirement. It was not indeed needed as part of the laboratory experiments.

'Check and Save' to show that any error was found. 

Adding the corresponding NMOS and PMOS models, the simulation can then be performed 

It is observed that the simulation matches the truth table. However, some glitches are shown in the output signals. Let's zoom in for a better look.

For XOR output signal, the glitch is generated due to the transition of the inputs from low to high (and high to low). This change in the inputs mean a voltage change in the gates. The voltage chagne (gnd to vdd or vdd to gnd) implies a transition form the accumulation region to strong inversion, and vice versa. Hence, this transition depends on the time it takes for the inputs to go from high to low or low to high. Consequently, to reduce the glitches, one must reduce the fall and rise time for the inputs. The following picture show the inputs and outputs signal for a fall and rise time of 100ps.

It is seen that the glitch was significantly reduced!

The last part of the laboratory experiments was to draft the schematic and symbol, layout, and LVS a full adder using NAND and XOR gates. The schematic and corresponding symbol are shown below.

Based on the schematic, the full adder is laid out by placing 5 gate end-to-end (3 NAND gates and 2 XOR gates).

The inputs (a, b, and cin) and output (s and cout) are pinned on metal2 layer. DRC to verify no errors were found.

Then, we can extract the layout.

LVS is then perfomed.

The netlists match! Now, we can use the full adder in a simulation to verify its corresponding truth table, as shown below

The schematic was simulated from 0 800nm. After adding the correponding NMOS and PMOS models, the simulation is shown below.

As always, back up of this lab was saved on my flashdrive and Google Drive account. Additionally, all the cell used in this lab can be downloaded here

Go back

Return to EE421L - Student Lab Reports

Return to EE421L - Fall 2015